522 search results - page 24 / 105 » A Note on Designing Logical Circuits Using SAT |
PATMOS
2005
Springer
14 years 25 days ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
ASPDAC
2005
ACM
14 years 27 days ago
2005
ACM
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
CEC
2003
IEEE
14 years 19 days ago
2003
IEEE
In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection an...