522 search results - page 35 / 105 » A Note on Designing Logical Circuits Using SAT |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
DELTA
2002
IEEE
14 years 10 days ago
2002
IEEE
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
ISQED
2005
IEEE
14 years 29 days ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...