522 search results - page 44 / 105 » A Note on Designing Logical Circuits Using SAT |
CIE
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. The input to a constraint satisfaction problem (CSP) consists of a set of variables, each with a domain, and constraints between these variables formulated by relations o...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
ICCD
1991
IEEE
13 years 11 months ago
1991
IEEE
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allow...
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...