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» A Note on Designing Logical Circuits Using SAT
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ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 11 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
VTS
2007
IEEE
100views Hardware» more  VTS 2007»
14 years 1 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
ISLPED
2009
ACM
118views Hardware» more  ISLPED 2009»
14 years 1 months ago
Serial sub-threshold circuits for ultra-low-power systems
This paper explores the use of serial circuits for ultra-low-power sub-threshold systems. A serial system leads to a smaller design and higher utilization, yielding 40% active ene...
Sudhanshu Khanna, Benton H. Calhoun
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 4 months ago
Novel dual-Vth independent-gate FinFET circuits
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
Masoud Rostami, Kartik Mohanram