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» A Note on Designing Logical Circuits Using SAT
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GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 6 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
ITC
2003
IEEE
148views Hardware» more  ITC 2003»
13 years 12 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
AC
2003
Springer
13 years 12 months ago
Synthesis of Asynchronous Hardware from Petri Nets
Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
Josep Carmona, Jordi Cortadella, Victor Khomenko, ...
CL
2000
Springer
13 years 11 months ago
Modelling Digital Circuits Problems with Set Constraints
A number of diagnostic and optimisation problems in Electronics Computer Aided Design have usually been handled either by specific tools or by mapping them into a general problem s...
Francisco Azevedo, Pedro Barahona
DAC
2009
ACM
14 years 7 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke