522 search results - page 76 / 105 » A Note on Designing Logical Circuits Using SAT |
120
Voted
GLVLSI
2008
IEEE
15 years 2 months ago
2008
IEEE
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
145
Voted
EUROGP
2009
Springer
15 years 7 months ago
2009
Springer
The contribution presented herein proposes an adaptive genetic algorithm applied to quantum logic circuit synthesis that, dynamically adjusts its control parameters. The adaptation...
128
Voted
FPGA
2000
ACM
15 years 6 months ago
2000
ACM
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
126
Voted
DAC
2001
ACM
16 years 3 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
99
Voted
FROCOS
2005
Springer
15 years 8 months ago
2005
Springer
We describe results and status of a sub project of the Verisoft [1] project. While the Verisoft project aims at verification of a complete computer system starting with hardware a...