522 search results - page 82 / 105 » A Note on Designing Logical Circuits Using SAT |
IJRR
2007
13 years 8 months ago
2007
— Haptics, like the fields of robotics and motion control, relies on high stiffness position control of electric motors. Traditionally DC motors are driven by current amplifier...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
CAL
2007
13 years 8 months ago
2007
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...