Exploiting die-to-die thermal coupling in 3D IC placement

In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are employed in a force-directed 3D placement successfully and outperform several state-of-the-art placers published in recent literature. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids—Placement and routing General Terms Algorithms, Design, Reliability Keywords 3D IC, TSV, Temperature

• Type: Journal
• Year: 2012
• Where: DAC
• Authors: Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
• Keywords: Computer Architecture, DAC 2012, Integrated Circuits Design, Literature Categories, Logic Cells