522 search results - page 84 / 105 » A Note on Designing Logical Circuits Using SAT |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
ISLPED
1999
ACM
14 years 9 days ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...