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» A Note on Designing Logical Circuits Using SAT
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DAC
2003
ACM
14 years 7 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...
IFIP
2001
Springer
13 years 11 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
ISMVL
2008
IEEE
160views Hardware» more  ISMVL 2008»
14 years 1 months ago
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean Sati...
Daniel Große, Robert Wille, Gerhard W. Dueck...
GLVLSI
2003
IEEE
145views VLSI» more  GLVLSI 2003»
14 years 6 hour ago
Using dynamic domino circuits in self-timed systems
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
Jung-Lin Yang, Erik Brunvand
AIA
2006
13 years 8 months ago
Speeding Up Model-based Diagnosis by a Heuristic Approach to Solving SAT
Model-based diagnosis of technical systems requires both a simulation machinery and a logic calculus. The former is responsible for the system's behavior analysis, the latter...
Benno Stein, Oliver Niggemann, Theodor Lettmann