Temporofunctional crosstalk noise analysis

Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design aids General Terms Algorithms, Reliability, Verification Keywords crosstalk noise, SAT formula, timed Boolean logic

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
• Keywords: DAC 2003, Delay Noise Faults, Design Automation, Keywords Crosstalk Noise, State-of-the-art Noise Analysis