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DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 17 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
BMCBI
2010
161views more  BMCBI 2010»
13 years 4 months ago
LTC: a novel algorithm to improve the efficiency of contig assembly for physical mapping in complex genomes
Background: Physical maps are the substrate of genome sequencing and map-based cloning and their construction relies on the accurate assembly of BAC clones into large contigs that...
Zeev Frenkel, Etienne Paux, David I. Mester, Cathe...
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
SLIP
2003
ACM
14 years 22 days ago
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
Navaratnasothie Selvakkumaran, Phiroze N. Parakh, ...
ISCAPDCS
2004
13 years 8 months ago
The Fat-Stack and Universal Routing in Interconnection Networks
This paper shows that a novel network called the fat-stack is universally efficient when adequate capacity distribution is provided and is suitable for use as an interconnection n...
Kevin F. Chen, Edwin Hsing-Mean Sha