Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays

Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS transistor of the downstream buffer to not turn fully off, this approach suffers from static power consumption and reduced noise margins. The standard pMOS transistor pull-up in an active feedback of an inverter reduces the static power consumption, but degrades the switching time and/or active power consumption. We propose a circuit technique to build level-restoring buffers, which improves the propagation delay or active power consumption at a tiny area penalty. Our main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the sl...

• Type: Conference
• Year: 2007
• Where: DSD
• Authors: Scott Miller, Mihai Sima, Michael McGuire
• Keywords: Downstream Buffer, DSD 2007, Hardware, Power Consumption, Static Power Consumption