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DAC
1996
ACM
15 years 8 months ago
Functional Verification Methodology of Chameleon Processor
- Functional verification of the new generation microprocessor developed by SGS-THOMSON Microelectronics makes extensive use of advanced technologies. This paper presents a global ...
Françoise Casaubieilh, Anthony McIsaac, Mik...
KBSE
2008
IEEE
15 years 10 months ago
Query-Aware Test Generation Using a Relational Constraint Solver
We present a novel approach for black-box testing of database management systems (DBMS) using the Alloy tool-set. Given a database schema and an SQL query as inputs, our approach ...
Shadi Abdul Khalek, Bassem Elkarablieh, Yai O. Lal...
IFIP
2001
Springer
15 years 8 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
152
Voted
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 8 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
KBSE
2002
IEEE
15 years 8 months ago
Generating Test Data for Functions with Pointer Inputs
Generating test inputs for a path in a function with integer and real parameters is an important but difficult problem. The problem becomes more difficult when pointers are pass...
Srinivas Visvanathan, Neelam Gupta