130 search results - page 4 / 26 » A Novel Metric for Interconnect Architecture Performance |
TPDS
2008
13 years 7 months ago
2008
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICC
2008
IEEE
14 years 2 months ago
2008
IEEE
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with i...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Despite recent advances in FPGA devices and embedded cores, their deployment in commercial products remains rather limited due to practical constraints on, for example, cost, size...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...