130 search results - page 7 / 26 » A Novel Metric for Interconnect Architecture Performance |
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
PPAM
2005
Springer
14 years 1 months ago
2005
Springer
The complexity and the dynamics of the Grid environment and of the emering workflow-based applications on the Grid require novel performance monitoring and analysis services in or...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
Large-scale systems like BlueGene/L are susceptible to a number of software and hardware failures that can affect system performance. Periodic application checkpointing is a commo...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...