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» A Novel Superscalar Architecture for Fast DCT Implementation
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ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
14 years 4 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
INTEGRATION
2007
100views more  INTEGRATION 2007»
13 years 7 months ago
A fast pipelined multi-mode DES architecture operating in IP representation
The Data Encryption Standard (DES) is a cipher that is still used in a broad range of applications, from smartcards, where it is often implemented as a tamperresistant embedded co...
Sylvain Guilley, Philippe Hoogvorst, Renaud Pacale...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 2 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
GLOBECOM
2007
IEEE
14 years 2 months ago
OBIG: the Architecture of an Output Buffered Switch with Input Groups for Large Switches
—Large, fast switches require novel approaches to architecture and scheduling. In this paper, we propose the Output Buffered Switch with Input Groups (OBIG). We present simulatio...
Wladek Olesinski, Hans Eberle, Nils Gura
IPPS
2002
IEEE
14 years 19 days ago
A SIMD Vectorizing Compiler for Digital Signal Processing Algorithms
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
Franz Franchetti, Markus Püschel