471 search results - page 37 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
IROS
2009
IEEE
14 years 3 months ago
2009
IEEE
— In this paper, we introduce a high-speed vision platform, H3 (Hiroshima Hyper Human) Vision, which can simultaneously process a 1024× 1024 pixel image at 1000 fps and a 256× ...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was present...
EUROPAR
2000
Springer
14 years 9 days ago
2000
Springer
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
DPHOTO
2009
13 years 6 months ago
2009
Under low illumination conditions, such as moonlight, there simply are not enough photons present to create a high quality color image with integration times that avoid camera-sha...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
— A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that relia...