471 search results - page 46 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
A motion adaptive de-interlacing algorithm and its hardware architecture are presented in this paper. It consists the directional interpolation - ELA with median processing, and 4...
DSD
2003
IEEE
14 years 2 months ago
2003
IEEE
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
ARITH
2007
IEEE
14 years 3 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
CG
2008
Springer
13 years 8 months ago
2008
Springer
Many volume data possess symmetric features that can be clearly observed, for example, those existing in diffusion tensor image data sets. The exploitations of symmetries for volu...