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» A Parallel Hardware Architecture for Image Feature Detection
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ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
14 years 2 months ago
Event-based imaging with active illumination in sensor networks
— We discuss a distributed imaging architecture with active illumination for sensor network applications. An event-based CMOS imager is employed at the sensor level, to convert l...
Eugenio Culurciello, Thiago Teixeira, Andreas G. A...
CODES
2001
IEEE
14 years 11 days ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
DATE
2010
IEEE
188views Hardware» more  DATE 2010»
14 years 1 months ago
Power-accuracy tradeoffs in human activity transition detection
— Wearable, mobile computing platforms are envisioned to be used in out-patient monitoring and care. These systems continuously perform signal filtering, transformations, and cla...
Jeffrey Boyd, Hari Sundaram, Aviral Shrivastava
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
14 years 2 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
ICIP
2006
IEEE
14 years 10 months ago
Image Compression using Object-Based Regions of Interest
A new architecture for region of interest (ROI) image coding is proposed. ROIs are defined as image regions containing objects of interest, and an efficient algorithm proposed for...
Sunhyoung Han, Nuno Vasconcelos