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» A Parallel Hardware Architecture for Image Feature Detection
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CGO
2007
IEEE
14 years 3 months ago
Loop Optimization using Hierarchical Compilation and Kernel Decomposition
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
Denis Barthou, Sébastien Donadio, Patrick C...
IPPS
2006
IEEE
14 years 2 months ago
Collective operations in NEC's high-performance MPI libraries
We give an overview of the algorithms and implementations in the high-performance MPI libraries MPI/SX and MPI/ES of some of the most important collective operations of MPI (the M...
Hubert Ritzdorf, Jesper Larsson Träff
HPCA
1999
IEEE
14 years 28 days ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
14 years 1 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
SI3D
1995
ACM
14 years 5 days ago
Real-Time Programmable Shading
One of the main techniques used by software renderers to produce stunningly realistic images is programmable shading—executing an arbitrarily complex program to compute the colo...
Anselmo Lastra, Steven Molnar, Marc Olano, Yulan W...