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» A Parallel Hardware Architecture for Image Feature Detection
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HPCA
2009
IEEE
14 years 3 months ago
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
Pablo Abad Fidalgo, Valentin Puente, José-&...
TROB
2002
244views more  TROB 2002»
13 years 8 months ago
Distributed surveillance and reconnaissance using multiple autonomous ATVs: CyberScout
The objective of the CyberScout project is to develop an autonomous surveillance and reconnaissance system using a network of all-terrain vehicles. In this paper, we focus on two f...
Mahesh Saptharishi, C. Spence Oliver, Christopher ...
HPCA
2008
IEEE
14 years 9 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
HPCA
2006
IEEE
14 years 9 months ago
LogTM: log-based transactional memory
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan...
HPCA
2008
IEEE
14 years 9 months ago
Performance-aware speculation control using wrong path usefulness prediction
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Pa...