31 search results - page 2 / 7 » A Parallel and Modular Architecture for 802.16e LDPC Codes |
SIPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we design block-structured LDPC codes for iterative MIMO receivers with soft sphere detection in particular channel environments. The receiver EXIT charts are used a...
TSP
2008
13 years 7 months ago
2008
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...