Sciweavers

26 search results - page 4 / 6
» A Performance Model of Communication in the Quarc NoC
Sort
View
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
DATE
2007
IEEE
113views Hardware» more  DATE 2007»
14 years 1 months ago
Congestion-controlled best-effort communication for networks-on-chip
Abstract. Congestion has negative effects on network performance. In this paper, a novel congestion control strategy is presented for Networks-on-Chip (NoC). For this purpose we in...
Jan Willem van den Brand, Calin Ciordas, Kees Goos...
ITNG
2008
IEEE
14 years 1 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
NOCS
2007
IEEE
14 years 1 months ago
Towards Open Network-on-Chip Benchmarks
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challe...
Cristian Grecu, André Ivanov, Partha Pratim...
ICCSA
2007
Springer
13 years 11 months ago
A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization
Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chi...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...