204 search results - page 18 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
WMPI
2004
ACM
14 years 29 days ago
2004
ACM
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computa...
FPL
2010
Springer
13 years 5 months ago
2010
Springer
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...