204 search results - page 36 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
HPDC
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, we present the design and implementation of Dodo, an e cient user-level system for harvesting idle memory in o -the-shelf clusters of workstations. Dodo enables dat...
SAMOS
2004
Springer
14 years 26 days ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
PPL
2008
13 years 7 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
SIGCOMM
2006
ACM
14 years 1 months ago
2006
ACM
There is a growing demand for network devices capable of examining the content of data packets in order to improve network security and provide application-specific services. Most...
JSA
2010
13 years 2 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...