204 search results - page 38 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
AAAI
1990
13 years 8 months ago
1990
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
USENIX
1994
13 years 8 months ago
1994
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...