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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 9 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
NPAR
2000
ACM
15 years 9 months ago
Stylized rendering techniques for scalable real-time 3D animation
Researchers in nonphotorealistic rendering (NPR) have investigated a variety of techniques to simulate the styles of artists. Recent work has resulted in methods for pen-and-ink i...
Adam Lake, Carl Marshall, Mark Harris, Marc Blacks...
CA
1999
IEEE
15 years 9 months ago
Collaborative Animation over the Network
The continuously increasing complexity of computer animationsmakes it necessary to rely on the knowledge of various experts to cover the different areas of computer graphics and a...
François Faure, Chris Faisstnauer, Gerd Hes...
ICRA
1999
IEEE
187views Robotics» more  ICRA 1999»
15 years 9 months ago
VISP: A Software Environment for Eye-in-Hand Visual Servoing
In this paper, we describe a modular software that allows fast development of eye-in-hand image-based visual servoing applications (ViSP states for "Visual Servoing Platform&...
Éric Marchand
FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
15 years 9 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...