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ICMCS
2006
IEEE
154views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Design of Audio and Video decoder for the T-DMB Receiver
We present a low-power architectural MPEG-4 part-10 AVC/H.264 video and MPEG-4 BSAC audio decoder chip capable of delivering high-quality and high-compression in wireless multimed...
Bontae Koo, Juhyun Lee, Sekho Lee, Jinkyu Kim, Min...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. ...
Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab
CF
2004
ACM
14 years 1 months ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 12 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...