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ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
14 years 5 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
KI
2006
Springer
13 years 8 months ago
Agent Logics as Program Logics: Grounding KARO
Abstract. Several options are available to relate agent logics to computational agent systems. Among others, one can try to find useful executable fragments of an agent logic or us...
Koen V. Hindriks, John-Jules Ch. Meyer
DLOG
2007
13 years 11 months ago
Blocking Automata for PSPACE DLs
In Description Logics (DLs), both tableau-based and automata-based algorithms are frequently used to show decidability and complexity results for basic inference problems such as c...
Franz Baader, Jan Hladik, Rafael Peñaloza
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
14 years 28 days ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
14 years 5 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...