Sciweavers

416 search results - page 12 / 84
» A Programming Approach to the Design of Asynchronous Logic B...
Sort
View
ASYNC
1999
IEEE
110views Hardware» more  ASYNC 1999»
14 years 1 months ago
Verification of Delayed-Reset Domino Circuits Using ATACS
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
AI
2004
Springer
13 years 8 months ago
ASSAT: computing answer sets of a logic program by SAT solvers
We propose a new translation from normal logic programs with constraints under the answer set semantics to propositional logic. Given a normal logic program, we show that by addin...
Fangzhen Lin, Yuting Zhao
DATE
1997
IEEE
75views Hardware» more  DATE 1997»
14 years 28 days ago
Using constraint logic programming in memory synthesis for general purpose computers
In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory ...
Renate Beckmann, Jürgen Herrmann
IJCAI
2001
13 years 10 months ago
Graph Theoretical Characterization and Computation of Answer Sets
We give a graph theoretical characterization of answer sets of normal logic programs. We show that there is a one-to-one correspondence between answer sets and a special, non-stan...
Thomas Linke
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
14 years 2 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...