Verification of Delayed-Reset Domino Circuits Using ATACS

This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self-resetting style since internally, a block of self-resetting or delayed-reset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The state-space explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of...

• Type: Conference
• Year: 1999
• Where: ASYNC
• Authors: Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
• Keywords: Analysis Tool Atacs, ASYNC 1999, Asynchronous Circuits, Delayed-reset Domino Circuits, Hardware