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ASYNC
2000
IEEE
181views Hardware» more  ASYNC 2000»
13 years 12 months ago
Asynchronous Design Using Commercial HDL Synthesis Tools
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
Michiel M. Ligthart, Karl Fant, Ross Smith, Alexan...
ISMVL
2010
IEEE
209views Hardware» more  ISMVL 2010»
14 years 19 days ago
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
—The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques ...
Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev
FPL
2009
Springer
99views Hardware» more  FPL 2009»
14 years 4 days ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
ENTCS
2002
125views more  ENTCS 2002»
13 years 7 months ago
Specification of Logic Programming Languages from Reusable Semantic Building Blocks
We present a Language Prototyping System that facilitates the modular development of interpreters from independent semantic buildks. The abstract syntax is modelled as the fixpoint...
José Emilio Labra Gayo, Juan Manuel Cueva L...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
14 years 29 days ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber