149 search results - page 11 / 30 » A Real-Time Streaming Memory Controller |
RTSS
2000
IEEE
14 years 1 days ago
2000
IEEE
The maturity of schedulabilty analysis techniquesfor fired-prioritypreemptive scheduling has enabled the consideration of timing issues at design time using a specification of the...
ICVS
2001
Springer
14 years 3 days ago
2001
Springer
Interactive robotics demands real-time visual information about the environment. Real time vision processing, however, places a heavy load on the robot’s limited resources, and m...
ECRTS
2006
IEEE
14 years 1 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
RTSS
2003
IEEE
14 years 28 days ago
2003
IEEE
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
RTSS
2007
IEEE
14 years 1 months ago
2007
IEEE
In multiprocessor systems, the traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers a...