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HPCA
2006
IEEE
14 years 8 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
ADHOCNETS
2010
Springer
13 years 4 months ago
DCLA: A Duty-Cycle Learning Algorithm for IEEE 802.15.4 Beacon-Enabled WSNs
The current specification for IEEE 802.15.4 beacon-enabled networks does not define how active and sleep schedules should be configured in order to achieve the optimal network perf...
Rodolfo de Paz Alberola, Dirk Pesch
AAAI
2000
13 years 9 months ago
Iterative Flattening: A Scalable Method for Solving Multi-Capacity Scheduling Problems
One challenge for research in constraint-based scheduling has been to produce scalable solution procedures under fairly general representational assumptions. Quite often, the comp...
Amedeo Cesta, Angelo Oddi, Stephen F. Smith
DAC
2005
ACM
14 years 8 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim
ICPPW
2007
IEEE
14 years 2 months ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu