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» A Reduced Complexity Algorithm for Minimizing N-Detect Tests
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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 7 days ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
ADBIS
2006
Springer
182views Database» more  ADBIS 2006»
14 years 20 days ago
A Middleware-Based Approach to Database Caching
Database caching supports declarative query processing close to the application. Using a full-fledged DBMS as cache manager, it enables the evaluation of specific project-select-...
Andreas Bühmann, Theo Härder, Christian ...
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 8 days ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
SMA
2003
ACM
173views Solid Modeling» more  SMA 2003»
13 years 12 months ago
Automating the CAD/CAE dimensional reduction process
Dimensional reduction is a simplification technique that eliminates one or more dimensions from a boundary value problem. It results in significant computational savings with mini...
Krishnan Suresh
BPM
2006
Springer
166views Business» more  BPM 2006»
13 years 10 months ago
Process Mining by Measuring Process Block Similarity
Mining, discovering, and integrating process-oriented services has attracted growing attention in the recent year. Workflow precedence graph and workflow block structures are two i...
Joonsoo Bae, James Caverlee, Ling Liu, Hua Yan