515 search results - page 56 / 103 » A Reduced Complexity Algorithm for Minimizing N-Detect Tests |
ICPR
2008
IEEE
14 years 9 months ago
2008
IEEE
This paper addresses the limitation of current multilinear PCA based techniques, in terms of prohibitive computational cost of testing and poor generalisation in some scenarios, w...
ITC
2002
IEEE
14 years 1 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ICRA
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— In this paper, we describe a method for coordinating multiple robots in a pursuit-evasion domain. We examine the problem of multiple robotic pursuers attempting to loca...
ICDM
2006
IEEE
14 years 2 months ago
2006
IEEE
Kernel methods have been shown to be very effective for applications requiring the modeling of structured objects. However kernels for structures usually are too computational dem...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...