154 search results - page 7 / 31 » A Register Allocation Technique Using Register Existence Gra... |
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of r...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
CC
2002
Springer
13 years 7 months ago
2002
Springer
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
INTEGRATION
2006
13 years 7 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...