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ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
14 years 2 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 2 months ago
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
14 years 2 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
AUSDM
2006
Springer
100views Data Mining» more  AUSDM 2006»
14 years 1 months ago
Data Mining Methodological Weaknesses and Suggested Fixes
Predictive accuracy claims should give explicit descriptions of the steps followed, with access to the code used. This allows referees and readers to check for common traps, and t...
John H. Maindonald
EMSOFT
2004
Springer
14 years 1 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha