Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
Petru Eles, Viacheslav Izosimov, Paul Pop, Zebo Pe...
We present an approach to recognizing faces with varying appearances which also considers the relative probability of occurrence for each appearance. We propose and demonstrate ex...
Nathan Mekuz, Christian Bauckhage, John K. Tsotsos
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Object recognition can be formulated as matching image features to model features. When recognition is exemplar-based, feature correspondence is one-to-one. However, segmentation e...
M. Fatih Demirci, Ali Shokoufandeh, Yakov Keselman...