317 search results - page 25 / 64 » A Scalable Architecture for Montgomery Multiplication |
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
ISQED
2010
IEEE
13 years 6 months ago
2010
IEEE
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...
JSAC
2006
13 years 7 months ago
2006
Abstract-- Information about the topology and link-level characteristics of a network is critical for many applications including network diagnostics and management. However, this ...