Sciweavers

237 search results - page 36 / 48
» A Scalable FPGA-based Multiprocessor
Sort
View
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 5 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
CCECE
2006
IEEE
14 years 2 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
ICS
2009
Tsinghua U.
14 years 1 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
CAL
2008
13 years 8 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
TC
2008
13 years 8 months ago
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Xiaogang Qiu, Michel Dubois