30 search results - page 1 / 6 » A Scalable Instruction Queue Design Using Dependence Chains |
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
SAC
2008
ACM
13 years 6 months ago
2008
ACM
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
IBMRD
2006
13 years 7 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
MICRO
2003
IEEE
14 years 19 days ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...