30 search results - page 6 / 6 » A Scalable Instruction Queue Design Using Dependence Chains |
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
ISPASS
2005
IEEE
14 years 28 days ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
14 years 7 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
RTSS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents the design of user-level scheduling hierarchies in the Composite component-based system. The motivation for this is centered around the design of a system that...
INFOCOM
2009
IEEE
14 years 2 months ago
2009
IEEE
—Network coding is a method that promises to achieve the min-cut capacity in multicasts. However, pushing towards this gain in throughput comes with two sacrifices. Delay suffer...