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DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
EUROMICRO
1999
IEEE
14 years 2 days ago
The X-MatchLITE FPGA-Based Data Compressor
This paper introduces a hardware amenable algorithm for lossless data compression and a highly integrable architecture which enables Gbit/s compression using contemporary ASIC tec...
Jose Luis Nunez, Claudia Feregrino, Simon Jones, S...
LCTRTS
2007
Springer
14 years 1 months ago
Hierarchical real-time garbage collection
Memory management is a critical issue for correctness and performance in real-time embedded systems. Recent work on real-time garbage collectors has shown that it is possible to p...
Filip Pizlo, Antony L. Hosking, Jan Vitek
RTCSA
2006
IEEE
14 years 1 months ago
Data Freshness and Overload Handling in Embedded Systems
In this paper we consider data freshness and overload handling in embedded systems. The requirements on data management and overload handling are derived from an engine control so...
Thomas Gustafsson, Jörgen Hansson
CODES
2008
IEEE
14 years 2 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid