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CODES
2006
IEEE
14 years 1 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
ICECCS
1998
IEEE
168views Hardware» more  ICECCS 1998»
14 years 2 hour ago
The Architecture Tradeoff Analysis Method
This paper presents the Architecture Tradeoff Analysis Method (ATAM), a structured technique for understanding the tradeoffs inherent in design. This method was developed to provi...
Rick Kazman, Mark H. Klein, Mario Barbacci, Thomas...
CASES
2004
ACM
13 years 11 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
CIDR
2009
140views Algorithms» more  CIDR 2009»
13 years 8 months ago
Energy Efficiency: The New Holy Grail of Data Management Systems Research
Energy costs are quickly rising in large-scale data centers and are soon projected to overtake the cost of hardware. As a result, data center operators have recently started turni...
Stavros Harizopoulos, Mehul A. Shah, Justin Meza, ...
IESS
2007
Springer
162views Hardware» more  IESS 2007»
14 years 1 months ago
Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs
Abstract This paper presents an embedded system design toolchain for automatic generation of parallel code runnable on symmetric multiprocessor systems from an initial sequential s...
Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, G...