1234 search results - page 204 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
IEEEPACT
2009
IEEE
13 years 5 months ago
2009
IEEE
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
COMPSAC
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Test cost minimisation approaches have traditionally been devoted to minimising "execution costs", while maximising coverage or reliability. However, in a runti...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
EVOW
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. Software configurable analogue arrays offer an intriguing platform for automated design by evolutionary algorithms. Like previous evolvable hardware experiments, these pl...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...