1234 search results - page 27 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
CGO
2008
IEEE
14 years 2 months ago
2008
IEEE
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met ...
IJES
2006
13 years 7 months ago
2006
Embedded real-time systems must satisfy not only logical functional requirements but also para-functional properties such as timeliness, Quality of Service (QoS) and reliability. W...
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Developing CPU scheduling algorithms and understanding their impact in practice can be difficult and time consuming due to the need to modify and test operating system ...