210 search results - page 10 / 42 » A Self-Reconfigurable Gate Array Architecture |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
JUCS
2000
13 years 7 months ago
2000
: Studying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to r...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
FCCM
2009
IEEE
13 years 11 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...