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» A Self-Reconfigurable Gate Array Architecture
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FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 4 days ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
13 years 11 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 2 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
ANCS
2005
ACM
14 years 1 months ago
A novel reconfigurable hardware architecture for IP address lookup
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel ...
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabae...
TIFS
2008
142views more  TIFS 2008»
13 years 7 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...